JPH0137019B2 - - Google Patents

Info

Publication number
JPH0137019B2
JPH0137019B2 JP58019187A JP1918783A JPH0137019B2 JP H0137019 B2 JPH0137019 B2 JP H0137019B2 JP 58019187 A JP58019187 A JP 58019187A JP 1918783 A JP1918783 A JP 1918783A JP H0137019 B2 JPH0137019 B2 JP H0137019B2
Authority
JP
Japan
Prior art keywords
data
received
register
detection circuit
interface circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58019187A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59144246A (ja
Inventor
Toshio Tsukui
Teruo Tobe
Kyoshi Washida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58019187A priority Critical patent/JPS59144246A/ja
Publication of JPS59144246A publication Critical patent/JPS59144246A/ja
Publication of JPH0137019B2 publication Critical patent/JPH0137019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
JP58019187A 1983-02-08 1983-02-08 デ−タ受信制御方式 Granted JPS59144246A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58019187A JPS59144246A (ja) 1983-02-08 1983-02-08 デ−タ受信制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58019187A JPS59144246A (ja) 1983-02-08 1983-02-08 デ−タ受信制御方式

Publications (2)

Publication Number Publication Date
JPS59144246A JPS59144246A (ja) 1984-08-18
JPH0137019B2 true JPH0137019B2 (en]) 1989-08-03

Family

ID=11992328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58019187A Granted JPS59144246A (ja) 1983-02-08 1983-02-08 デ−タ受信制御方式

Country Status (1)

Country Link
JP (1) JPS59144246A (en])

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61264829A (ja) * 1985-05-17 1986-11-22 Fujitsu Ltd ネツトワ−ク制御装置の割込み制御方式
JPH0516619U (ja) * 1991-08-06 1993-03-02 大日本印刷株式会社 クラツシユ機能を有するカートン

Also Published As

Publication number Publication date
JPS59144246A (ja) 1984-08-18

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